Altera adds Floating Point feature to Gate Arrays
Altera have announced they are the first FPGA producer to implement hardened IEEE 754 compliant, floating-point operators in their Arria 10 and Stratix 10 families of FPGAs. The IEEE 754 pipe comes as an addition to the 18b and 27b fixed point math pipes already available in the DSP. The 20 nm Arria 10 can also include a dual-core hard ARM Cortex-A9, serial transceivers up to 28.3 Gbit/s, backplane support up to 17.4G bit/s and support for DDR4 at 2.666 Gbit/s
The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, the hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. The technology enables Altera to deliver up to 1.5 TeraFLOPs DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices. This now gives DSP designers the choice of either fixed or floating-point modes. The floating point blocks are backwards compatible with existing designs.
According to Altera’s director of software Alex Grbic “The implementation of IEEE 754-compliant floating-point DSP blocks in our devices is truly a game-changer for FPGAs, it gives Altera FPGAs and SoCs a performance and power efficiency advantage over microprocessors and GPUs in an expanded range of applications.” The hardened floating point DSP blocks are already implemented in Arria 10 and Stratix 10 families shipping today but the company will not be releasing the code necessary to enable the feature until later this year.
