Smarter routing achieves faster FFT
Researchers working at Linköping University in Sweden have developed an optimization process to give a five-fold boost in processing speed of a standard algorithm implemented in an FPGA...
Researchers working at Linköping University in Sweden have developed an optimization process to give a five-fold boost in processing speed of a standard algorithm implemented in an FPGA.
When it comes to high-speed real-time signal processing applications it's often necessary to use a Fast Fourier Transform algorithm to give the Discrete Fourier Transform of a signal. This can be implemented in software or hardware, for speed its better to use hardware because many of the processing tasks can more easily be implemented in parallel.
The hardware will usually consist of an FPGA, according to researcher Carl Ingemarsson “Normally, you choose an algorithm that can carry out the desired calculations, and then build up the structure, the architecture, using the required blocks. This is then transferred to the FPGA. But we have also looked at how the logic is built up, the routes the signals take, and what happens to them inside the chip. We have then adapted the architecture and the mapping onto the chip using the results of this analysis.” By optimising the signal paths in the FPLA he was able to clock the chip at 450 MHz which is five times that of the standard FFT configuration.
According to the press release Carl, along with his wife is also planning to start a microbrewery. He hopes to celebrate with friends; swilling beer he brewed himself when his thesis is finally presented. We wholeheartedly applaud his meticulous efforts.
When it comes to high-speed real-time signal processing applications it's often necessary to use a Fast Fourier Transform algorithm to give the Discrete Fourier Transform of a signal. This can be implemented in software or hardware, for speed its better to use hardware because many of the processing tasks can more easily be implemented in parallel.
The hardware will usually consist of an FPGA, according to researcher Carl Ingemarsson “Normally, you choose an algorithm that can carry out the desired calculations, and then build up the structure, the architecture, using the required blocks. This is then transferred to the FPGA. But we have also looked at how the logic is built up, the routes the signals take, and what happens to them inside the chip. We have then adapted the architecture and the mapping onto the chip using the results of this analysis.” By optimising the signal paths in the FPLA he was able to clock the chip at 450 MHz which is five times that of the standard FFT configuration.
According to the press release Carl, along with his wife is also planning to start a microbrewery. He hopes to celebrate with friends; swilling beer he brewed himself when his thesis is finally presented. We wholeheartedly applaud his meticulous efforts.
