6809 DRAM controller

elektor july/august 1983 91 H. Fischer E n RFSH e•lo pno RAS JE.10 Eno 6809 DRAM controller CAS 1,2 E•20 ADDR * Data Read Cycle 0.30 coifAdd. 0.,0 c This circuit of a Random Access Memory controller is a real treat for owners of a 6809. It enables at least 128 k bytes of a dynamic RAM to be addressed and even then it has some spare capacity. 2 The controller cannot be used for chips other than the 6809 as it makes use of a special feature of that particular processor. The memory refresh is produced by timing signals from the microprocessor E and Q. AnORfunctionwiththesetwosig- A2=0 0 nals is performed by gates N2, N3 and N10,andthetimingdiagram is shown the address bus. It is almost impossible to show this correlation clearly, but the matter in figure 3. The circuit of figure 1 shows only two of the eight memory ICs (4164); the corresponding signals must, of course, be fed to each of the 16 KO A6 K1 A16 K1 83544.2 5V+ 7-90 E 0 AO o-- Ic1 1C4 cl 2x cz 4164 C!— Ais R/W p cS0- ...