Keysight Technologies, Inc., a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to connect and secure the world, announced a comprehensive workflow solution - PathWave Advanced Design System (ADS) 2022 -  that reduces design time and de-risks product development for Double Data Rate 5 (DDR5),  Low-Power Double Data Rate (LPDDR5) and Graphics Double Data Rate 6 (GDDR6) memory systems.

From cloud computing to autonomous vehicles, the demand for faster memory interfaces is accelerating.  A disruptive technology feature of fast interfaces such as DDR5, LPDDR5 and GDDR6 is equalization on the memory chip’s receivers, which recovers signals degraded by their path through the printed circuit board (PCB). Hardware engineers need to minimize the risk of signal integrity issues in memory bus designs, which requires the ability to predict the signal quality after equalization, prototype the design and test for performance.
 
PathWave Advanced Design System
PathWave ADS 2022 simulating DDR5 signals with equalization, designing signal vias, and performing electromagnetic simulation of the DDR signal nets in a PCB design


Keysight’s PathWave ADS 2022, a design and test workflow for next-generation memory, enables hardware engineers to meet time-to-market requirements and deliver a high-performance, reliable end-product. The Memory Designer in PathWave ADS 2022, addresses the following design challenges:  
  • Model the transmitter and receiver behavior accurately by generating advanced simulation models of both DDR transmitters and receivers, with flexible equalization and external clock inputs.
  • Optimize equalization settings to predict design margins with an advanced simulator that uses adaptive equalization to find the optimal settings for the best signal integrity of the data link. 
  • Quantify margin to the eye-mask by predicting eye closure down to standard-specific Bit-Error-Rates, and report remaining margin to the eye-mask.
  • Find failing conditions with design exploration by generating a batch simulation list to sweep through all possible design parameters and report passing/failing configurations as spreadsheet data.
  • Confidence in design sign-off, from design through to test by performing an automated compliance report on simulated signal waveforms and utilizing consistent measurement science to identify issues early and trial potential fixes efficiently.   

“PathWave ADS’ leading-edge signal integrity simulator helps Xilinx in our advanced system memory development. Working with Keysight, we’re able to optimize system memory solutions for our customers,” said Thomas To, director of System Memory SI at Xilinx.
 
“DDR5 is a revolutionary technology, requiring designers to re-assess their simulation and measurement approaches,” stated Brig Asay, director of Strategic Planning – Internet Infrastructure Group at Keysight. “Keysight’s knowledge in both DDR5 simulation and measurement techniques, enables us to help customers through this technology hurdle, and speed them to a first-pass design success.”