Article

The SCCC Project (4)

Homebrew soft-core processor and C compiler

In this installment we will look at how to output analogue signals with the help of sigma-delta DACs (digital-to-analogue converters) and interrupts.

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Materials

The SCCC Project (1), ElektorLabs magazine 2/2019

The SCCC Project (2), ElektorLabs magazine 3/2019

The SCCC Project (3), ElektorLabs magazine 4/2019

Project page accompanying this article

Discussion (0 comments)

Gnat 5 years ago

I have been surprised that the built-in MAX1000 USB-serial ttl has not been used.

The modifiacations described below show how to replace the use of an external serial interface on PMOD7 and PMOD8 with the built-in interface.

Also included is a psuedo random number generator that generates usable RF noise to over 30MHz on PMOD5.
Later, this noise source will be switched on and off under CPU control, by an outA instruction.

Changes to proj7TopLevel1v01.qsf

#proj7TopLevel1v01.qsf

#Before line:
#set_global_assignment -name VERILOG_FILE Counter1.v

#add the following:
#============================================================
# UART
#============================================================
set_location_assignment PIN_A4 -to BDB0
set_location_assignment PIN_B4 -to BDB1
set_location_assignment PIN_B5 -to BDB2
set_location_assignment PIN_A6 -to BDB3
set_location_assignment PIN_B6 -to BDB4
set_location_assignment PIN_A7 -to BDB5
# TXD : BDB0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDB0
# RXD : BDB1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDB1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDB2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDB3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDB4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDB5
#============================================================

set_global_assignment -name VERILOG_FILE Noisegen.v

Changes to TopLevel1v01.v

//TopLevel1v01.v

//1. Replace external serial interface on PMOD7 and PMOD8 with the built-in MAX1000 FTDI
//2. Add a pseudo noise generator with output to 30MHz plus, for filter and radio testing

//- Add following code ( "," is necessary after  "output LISsenSDI" :
//module TopLevel1v01 (
//  input  CLK12M  ........  output LISsenSDI,  

  input   BDB0,
  output  BDB1,
  input   BDB2,
  output  BDB3,
  input   BDB4,
  output  BDB5
  
  //  input   Input_only
);

//- Change the assigment statements:
assign sCuartRXpin=~BDB0;          ///PMOD8 ;      ////#### signal inverted for FTDI
assign BDB1=~sCuartTXpin ;         ///PMOD7=sCuartTXpin ;      ////#### signal inverted for FTDI

assign PMOD5= pbrs_noise ;    //PWM0pin ;

//- Add instantiation of the psuedo random noise generator:

// *************************************************************************************
wire pbrs_clk;
wire pbrs_noise;

pbrs #(.pbrswidth(23), .pbrstap1(23) , .pbrstap2(18)) pbrs_noise_inst( 
  .s_clk(pbrs_clk),
  .noise(pbrs_noise)
  );

assign pbrs_clk = clk_100;  //CLK12M;
  
// *************************************************************************************

Include this new module in /experiment5/experiment5/Noisegen.v



/* PRBS generator references
   -RADCOM July 2018 p66 Design Notes Andy Talbot: Wideband noise as a test source:
   -Wireless World February 1975 p87 Pseudo-random binary sequence generators F.Butler
	   with table of sequences and taps up to 15 bits.

	When clk is 100MHz, comb size for 23 bits = 2**23-1 = 8388607 => 11.9Hz
*/

module pbrs #(parameter pbrswidth=23, parameter pbrstap1=23 , parameter pbrstap2=18)( 
  input  wire  s_clk,
  output wire  noise
  );


reg  [pbrswidth:1]  pbrs_shift ;

wire   fb;
assign fb = pbrs_shift[pbrstap1] ^ pbrs_shift[pbrstap2] ;

assign noise = ~pbrs_shift[pbrswidth] ;

always @(posedge s_clk) begin
    pbrs_shift <= {pbrs_shift[pbrswidth-1:1],~fb };
  end

endmodule