high resolution colour graphics card (part 3) - The third instalment of an article describing a 512x512 or 512x256 pixel, black Et- white or colour, graphics card.

high resolution colour graphics card 3 by P Lavigne a- D Meyer Circuit description Address decoding The eight most significant address lines, A8 . A 15 in Fig. 15, are applied to the P- inputs of 8-bit comparator IC1. The Q-inputs of this IC are polarized by resistors R1 . .R8 and switches S1 . . S8. When the most significant address byte on the bus is the same as the binary word programmed by the user with Si . . S5, output P=Q of IC1 goes low, which enables IC2 to read address lines A4 . . A7. Since address line A7 is tied to enable input G2A of IC2, this circuit is active only for addresses between XX0 and XX7y, where XX is defined by A8. . A15 of IC1 and Y by IC3. Note that the presence of 4)2 on enable input G1 of IC2 ensures that the address decoding is synchronized with the signals of the 6502. Of the eight outputs of IC2, only two are used, each of which defines a block of six- teen addresses. One activates the GDP"s E(nable) input so that this is decoded between XX50 and ...