There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression parts, and EMI simulation design. This article starts with the most basic PCB layout, discusses the role and design skills of PCB layered stack-up in controlling EMI radiation.

Electricity Busbar

Reasonably placing a capacitor of appropriate capacity near the power supply pin of the IC can make the output voltage of the IC jump faster. However, the problem does not end there. Due to the limited frequency response of the capacitor, this makes it impossible for the capacitor to generate the harmonic power required to cleanly drive the output of the IC over the entire frequency band. In addition, the transient voltages formed on the electricity busbar will form a voltage drop across the inductance of the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

As far as the IC on our circuit board is concerned, the power supply layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of a good power layer should be small, so the transient signal synthesized by the inductor is also small, which reduces the common-mode EMI.

Of course, the wiring from the power supply layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, it is best to connect directly to the pad where the IC power pin is located, which is discussed separately.

In order to control common-mode EMI, the power layer must help to decouple and have sufficiently low inductance. This power layer must be a fairly well-designed power layer pair. Someone may ask, to what extent is it good? The answer to the question depends on the layering of the power supply, the materials between the layers, and the operating frequency (a function of IC rise time). In general, the power layer spacing is 6mil, and the interlayer is FR4 material. The equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of IC, devices with a rise time in the range of 100 to 300 ps will occupy a high proportion. For circuits with rising times of 100 to 300 ps, 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use a layering technique with a layer spacing of less than 1 mil and replace the FR4 dielectric material with a high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300 ps rise time circuits.

Although new materials and methods may be adopted in the future, for today's 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, it is usually enough to handle high-end harmonics and keep transient signals low enough, That said, common-mode EMI can be reduced very low. The PCB layered stack-up design example given in this article will assume a layer spacing of 3 to 6 mils.

Electromagnetic Shielding

From the perspective of signal traces, a good layering strategy should be to place all signal traces on one or more layers, which are next to the power or ground layers. For the power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the "layering" strategy.

PCB Stack-up

What stack-up strategy can help shield and suppress EMI? The following layered stack-up scheme assumes that the supply current flows on a single layer and that a single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power planes is discussed later.

4-layer board

There are several potential problems with the 4-layer board design. First, with a traditional four-layer board with a thickness of 62 mils, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If cost requirements are paramount, the following two alternatives to traditional 4-layer boards can be considered. Both of these solutions can improve the performance of EMI suppression, but they are only applicable to the situation where the component density on the board is low enough and there is enough area around the component (place the required power copper layer).

The first is the preferred solution. The outer layers of the PCB are ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is routed with wide wires, which can make the path impedance of the power supply current low and the impedance of the signal microstrip path low. From an EMI control perspective, this is the best 4-layer PCB structure available. The outer layer of the second scheme uses power and ground, and the middle two layers use signals. Compared with the traditional 4-layer board, this solution has a smaller improvement, and the interlayer impedance is not as good as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking schemes must be very careful to place the traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as much as possible to ensure DC and low-frequency connectivity.