Key standards to bear in mind
To first step when addressing ESD should always be to ensure that any electronic component is compliant with the latest international standards.
The requirements for tackling ESD are set out in IEC 61340-5-1 and methods are specified in IEC 61340-5-2 as the user guide.
IEC 61000-4-2 outlines the testing for simulating ESD from the human body at different levels, through both contact and air discharge.
 
Level Test Voltage (Contact Discharge) Test Voltage (Air Discharge)
1 2kV 2kV
2 4kV 4kV
3 6kV 8kV
4 8kV 15kV
 
For chip makers, IEC 60749-28:2017(E) sets out the procedure for testing, evaluating, and classifying chips according to their susceptibility to damage from an induced charged-device-model (CDM) ESD. All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs) and multi-chip modules (MCMs) containing any of these devices have to be evaluated according to this standard and tested in a package similar to the final application. This helps reassure assemblers that the parts are fully reliable, but does not absolve them of responsibility for ensuring that the parts are treated with care.
In the US the ANSI/ESD S20.20-2014 Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices) standard provides the technical requirements for an ESD Control Program for discharges over 100 V.