Microchip Enters Memory Infrastructure Market with Serial Memory Controller for High-performance Data Center Computing
“Microchip is excited to introduce the industry’s first serial memory controller device to the market,” said Pete Hazen, vice president of Microchip’s Data Center Solutions business unit. “New memory interface technologies such as Open Memory Interface (OMI) enable a broad range of SoC applications to support the increasing memory requirements of high-performance data center applications. Microchip’s entrance into the memory infrastructure market underscores our commitment to improving performance and efficiency in the data center.”
“IBM customer workload requirements are increasingly memory-intensive, which is why we have made the strategic decision for POWER processor memory interfaces to utilize OMI standard interfaces to increase memory bandwidth,” said Steve Fields, chief architect of IBM Power Systems. “IBM appreciates the partnership with Microchip to deliver this solution.”
SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin DDR4 Differential Dual-Inline Memory Modules (DDIMM) with capacities ranging from 16 GB to 256 GB. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly plug into any OMI-compliant 25 Gbps interface.
Quotes
“The Open Memory Interface (OMI) standard delivers a pin-efficient serial memory interface so a broad range of CPU and SoC applications can both scale memory bandwidth and seamlessly transition between an increasing number of emerging media types such as storage class memory,” said Myron Slota, president of the OpenCAPI Consortium. “The OpenCAPI consortium provides royalty-free host and target IP, as well as drives a broad set of initiatives to ensure standards compliance.”
“Google customers benefit from data intensive applications such as machine learning and data analytics that require high performance memory,” says Rob Sprinkle, technical lead for platforms infrastructure at Google LLC. “Google strongly supports open standards-based initiatives such as the Open Memory Interface (OMI), which provides a high-performance memory interface to meet these important bandwidth and latency performance goals.”
Development Tools
To support customers building systems that are compliant with the OMI standard, the SMC 1000 comes with design-in collateral and ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive GUI.
Pricing and Availability
The SMC 1000 8x25G is sampling now. For additional information, visit https://www.microchip.com/smartmemory.
“IBM customer workload requirements are increasingly memory-intensive, which is why we have made the strategic decision for POWER processor memory interfaces to utilize OMI standard interfaces to increase memory bandwidth,” said Steve Fields, chief architect of IBM Power Systems. “IBM appreciates the partnership with Microchip to deliver this solution.”
SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin DDR4 Differential Dual-Inline Memory Modules (DDIMM) with capacities ranging from 16 GB to 256 GB. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly plug into any OMI-compliant 25 Gbps interface.
Quotes
“The Open Memory Interface (OMI) standard delivers a pin-efficient serial memory interface so a broad range of CPU and SoC applications can both scale memory bandwidth and seamlessly transition between an increasing number of emerging media types such as storage class memory,” said Myron Slota, president of the OpenCAPI Consortium. “The OpenCAPI consortium provides royalty-free host and target IP, as well as drives a broad set of initiatives to ensure standards compliance.”
“Google customers benefit from data intensive applications such as machine learning and data analytics that require high performance memory,” says Rob Sprinkle, technical lead for platforms infrastructure at Google LLC. “Google strongly supports open standards-based initiatives such as the Open Memory Interface (OMI), which provides a high-performance memory interface to meet these important bandwidth and latency performance goals.”
Development Tools
To support customers building systems that are compliant with the OMI standard, the SMC 1000 comes with design-in collateral and ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive GUI.
Pricing and Availability
The SMC 1000 8x25G is sampling now. For additional information, visit https://www.microchip.com/smartmemory.
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